1. Field of the Invention
The present invention relates to a DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform) processor as a coding system extensively used in a digital signal process (DSP) field and a voice/image compression system field, and more particularly, to a DCT/IDCT processor capable of improving a DCT/IDCT processing speed and performing a DCT and an IDCT by one processor to thereby enable to embody a very large scale integrated circuit (VLSI).
2. Discussion of Related Art
Generally, in new digital video systems such as a set-top digital cable television box, a direct broadcast satellite (DBS) television, a terrestrial digital television, a digital video disk player (DVDP), a conversational television, a video on demand (VOD) and a video network server, these systems quite depend upon an effective image compression.
The image compression is embodied through a preprocessing step for the sake of an effective process in a succeeding coding, a sub-sampling step for largely lessening the quantity of information, a predicting step by using a spacial correlation among adjacent pixels and a time correlation on a moving image, an orthogonal transform step for reducing the quantity of information by removing a correlation among samples and biasing the distribution for an appearance frequency of sample values, a quantization step for substituting data of successive quantity by discrete values, and an entropy coding step for coding signals gained by the preprocessing into bits of small quantities.
The orthogonal transform is as a transform that the transformed matrix is an orthogonal matrix, wherein the orthogonal matrix is as a matrix that respective rows and columns are orthogonal each other among square matrixes and its respective magnitude is `1`. Such orthogonal matrix has some nature, in which an input signal having a high correlation is changed to a signal having a low correlation. That is, data from a result gained by multiplying this matrix by an input vector becomes a low correlation therein. There also is a characteristic that, in a signal flowchart of a provided orthogonal transform, a signal flowchart for its inverse transform is gotten by inverting an arrow mark of a forward signal flowchart. Such orthogonal transform is used in various fields, e.g., an image process field, especially an image data compression. The orthogonal transform further has a Karhunen-Loeve transform using an inherent value vector, a discrete cosine transform and a Walsh-Hadamard transform (WHT).
The DCT/IDCT requires considerably much process time in a compression and restoration system of real time information, thus through an elevation of such partial performance a systematic performance in an overall-video compression and restoration system can be improved.
The (JPEG Joint Photographic Experts Group) as an international standard group in a digital compression of a still picture containing a gray scale and a color picture recommends four operating modes in supporting various application fields. Among four operating modes a compression algorithm based on the DCT/IDCT is provided as a standard item in a sequential coding more, a progressive coding mode and a hierarchical coding more, excepting a lossless compression.
As shown in FIG. 1, conventionally, a two dimensional IDCT processor in such orthogonal transform, namely the "VLSI executive IDCT processor" provided by U.S. Ser. No. 8/520,044, is composed of a prescaler 11 for inputting DCT coefficients and performing a prescaling therefor: a multiplexer 12 for leading DCT correlation coefficient data prescaled in the prescaler 11 to an inputter of a matrix multiplier 13; the matrix multiplier 13 for multiplying each row of the prescaled DCT correlation coefficient matrix inputted from the multiplexer 12 by an IDCT correlation coefficient matrix; a standardization and round-off part 14 for providing a bit correctness proper to an intermediate output matrix outputted from the matrix multiplier 13; a transpose buffer 15 for transposing the intermediate output matrix scaled and rounded off in the standardization and round-off part 14 to thereby send the matrix to the multiplexer 12; a final standardization and round-off part 16 for providing the bit correctness appropriate for a final output matrix outputted from the matrix multiplier 13; and a block buffer 17 for buffering data gained from the final standardization and round-off part 16 and outputting final IDCT data.
The matrix multiplier 13, as shown in FIG. 2, includes a vector multiplier 23 having a plurality of registers 24, 26 and a fixed positional multiplier 25, for executing a vector multiplication; and an accumulator 27 having numerous registers 29, 30, 33, an accumulating unit 28, an addition unit 31 and a deduction unit 32, for accumulating data.
In reference numbers of FIG. 2, 21 is a data path of an odd channel, 22 is a data path of an even channel, 34 and 35 are crossbar switches for performing an interface between the vector multiplier 23 and the accumulator 27, and 36 and 37 are multiplexers for executing an interface among the accumulating unit 28, the addition unit 31 and the deduction unit 32.
Operations of the two dimensional IDCT processor based on the conventional technique under such construction are described in detail referring to the accompanied diagrams, as follows.
In an image compressing technique based on the DCT, the DCT is done by using, as a unit, a block constructed from 64 pixel samples of `8.times.8` for data inputted to an encoder. Then a decoder reconstructs it as original image information through an IDCT to thereby gain a reproduction image of `8.times.8`.
In order to get the above-mentioned result, the prescaler 11 receives the DCT coefficients to then perform the prescaling and sends the coefficients to the multiplexer 12, and the multiplexer 12 inducts the prescaled DCT correlation coefficient data to the inputter of the matrix multiplier 13.
The vector multiplier 23 of the matrix multiplier 13 multiplies each row of the prescaled DCT correlation coefficient matrix inputted from the multiplexer 12 by the IDCT correlation coefficient matrix, and the accumulator 27 thereof stores its matrix data.
The standardization and round-off part 14 provides the bit correctness proper to the intermediate output matrix outputted from the matrix multiplier 13, and the transpose buffer 15 transposes the intermediate output matrix scaled and rounded off in the standardization and round-off part 14 to thereby send the matrix to the multiplexer 12. The matrix multiplier 13 again multiplies each row of the DCT correlation coefficient matrix by the IDCT correlation coefficient matrix and stores the matrix from its result.
The final standardization and round-off part 16 provides the adequate bit correctness for the final output matrix outputted from the matrix multiplier 13, and then the block buffer 17 outputs the DCT coefficients.
This IDCT processor is optimized so as to be used within an MPEG-2 decoder, in other words, the IDCT processor operates on MPEG data based on an 8.times.8 block. The IDCT processor carries out a procedure of a rapid two-dimensional eight-points IDCT calculation, and an input matrix of the two dimensional DCT coefficients is prescaled. This prescaled matrix is applied to the matrix multiplier 13 in which specific two-dimensional IDCT correlation coefficient matrixes are multiplied by a row-to-row system, so as to accumulate the intermediate output matrixes. Such intermediate output matrixes are applied to a transpose memory having transpose values of the output matrixes. Then, the matrix multiplier 13 multiplies the specific two-dimensional output matrix by a transposed output matrix in the row-to-row system, and accumulates its result matrixes. The specific two-dimensional correlation coefficient matrix and the prescaled correlation coefficients are selected so that its result matrix is approximate to the IDCT of input DCT correlation coefficients and the two-dimensional correlation coefficient matrix contains only five specific values any one of which is `1`.
As afore-mentioned, many DCT/IDCT operations are followed in the MPEG encoder and decoder used in the encoder of the digital video system and the decoder of a receiving apparatus. For example, in case an image frame is displayed 30 frames/sec in an MPEG (Moving Picture Experts Group) 2, one ASIC is available to be embodied when the DCT in the encoder is only performed at a speed of `1920.times.1080.times.(6/4).times.30=93.312 MPixel/sec`. Further, it should be equipped the IDCT processor in the decoder in order to reproduce original image data.
Meanwhile, the DCT and IDCT processors applied to such conventional MPEG encoder and decoder have a mutual similar structure, and there is in an image transmitting/receiving system a shortcoming that the DCT and IDCT processors having the similar structure should be respectively installed in the encoder and the decoder. In such case, a size of the system becomes also relatively large due to an installment of two processors.